The present invention relates to CMOS switching circuitry, and more specifically but not exclusively to CMOS level shift circuitry.
The art is replete with level shift circuitry providing an output at a different voltage level to the input.
In an integrated circuit using CMOS technology it is desirable to use p FETs and n FETS. A difficulty may arise in that the relative current carrying ability of the p FETs and n FETs may vary from chip-to-chip. Where the level shifting circuitry requires a particular relationship between p FETs and n FETs to operate properly, difficulties may arise. For example, where the pull-up of an output node is provided by a p FET and the pull-down by an n FET the circuit may operate too slowly under certain tolerance conditions.
It is accordingly an object of the present invention to at least partially mitigate the difficulties of the prior art.
According to a first aspect of the present invention there is provided a CMOS switching circuit comprising input circuitry and output circuitry, said input circuitry having a first input switch and a second input switch, each input switch being connected to an input terminal, a pair of cross-coupled CMOS inverters forming bistable circuitry, said bistable circuitry connectable to a power terminal and having a first and a second branch, said first branch being connectable to a reference terminal via said first input switch and said second branch being connectable to said reference terminal via said second input switch, said output circuitry being connected to said bistable circuitry for providing a circuit output.
Preferably said first input switch has a control node coupled directly to said input terminal and said second switch has a control node coupled to said input terminal via a first inverter, whereby drive to said input switches is complementary.
Advantageously each of said CMOS inverters has a respective common gate, the common gate of the CMOS inverter of the first branch and the common gate of the CMOS inverter of the second branch being connected to said output circuitry.
Conveniently the two CMOS inverters have a common source terminal connectable to said power terminal via a power switch.
Advantageously said power switch is a p FET.
Advantageously the output circuitry comprises an output p FET having a gate coupled to the common gate of said CMOS inverter of the first branch via a further inverter, and an output n FET having a gate coupled to the common gate of said CMOS inverter of the second branch, the output p FET and the output n FET having a common source/drain terminal.
Preferably the common gates of the CMOS inverters of said first and second branches are connected to said reference terminal via respective equalization switches.
Advantageously said common source/drain terminal is connected to a circuit output terminal via cross-coupled output inverters.
Conveniently the cross-coupled output inverters comprise a forward inverter and a relatively weak feedback inverter.
Conveniently the power switch has a control node connected in common with the control nodes of the equalization switches.
Preferably a voltage supply to said input circuitry differs from a voltage supply to said output circuitry whereby said circuit output is level shifted.
An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawing which shows a schematic diagram of an embodiment of a CMOS switching circuit in accordance with the invention.